A highly digital MDLL-B ased clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance

  • Helal B
  • Straayer M
  • Wei G
 et al. 
  • 57


    Mendeley users who have this article in their library.
  • 61


    Citations of this article.


This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 mum integrated circuits, which have a combined active area of 0.06 mm2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

Author-supplied keywords

  • Correlated double sampling
  • Correlation
  • Deterministic jitter
  • First-order noise shaping
  • Gated ring oscillator (GRO)
  • Multiplying delay-locked loop (MDLL)
  • Reference spur
  • Scrambling
  • Time-to-digital converter (TDC)

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document


  • Belal M. Helal

  • Matthew Z. Straayer

  • Gu Yeon Wei

  • Michael H. Perrott

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free