This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopie capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-μW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-μm CMOS process with 6.2 mW. © 2006 IEEE.
CITATION STYLE
Xie, X., Li, G., Chen, X., Li, X., & Wang, Z. (2006). A low-power digital IC design inside the wireless endoscopic capsule. In IEEE Journal of Solid-State Circuits (Vol. 41, pp. 2390–2400). https://doi.org/10.1109/JSSC.2006.882884
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