A New Solution to Coherence Problems in Multicache Systems

Abstract

A memory hierarchy has coherence problems as soon as one of its levels is split in several independent units which are not equally accessible from faster levels or processors. The classical solution to these problems, as found for instance in multiprocessor, multicache systems, is to restore a degree of interdependence between such units through a set of high speed interconnecting buses. This solution is not entirely satisfactory, as it tends to reduce the throughput of the memory hierarchy and to increase its cost. A new solution is presented and discussed here: the presence flag solution. It has both a lower cost and a lower overhead than the classical solution. A very important feature of this solution is that it is possible, in a cache-main memory subsystem, to delay updating the main memory until a block is needed in the cache (nonstore-through mode of operation). Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.