Performance limitations of graphene nanoribbon tunneling FETS due to line edge roughness

Abstract

The functionality of tunneling field-effect transistors (TFETs) with a subthreshold slope SS better than 60 mV/dec at room temperature has recently been experimentally demonstrated [1, 2]. TFETs based on graphene nanoribbon (GNR) are expected to offer larger ON-currents, lower OFF-currents, and steeper SS than Si or III-V compound semiconductors, they are one-dimensional, fully compatible with planar processing, and they have light and identical conduction and valence effective masses as well as a width-tunable narrow band [3, 4]. However, it seems rather difficult to perfectly control the width of sub-10-nm GNRs and avoid line edge roughness (LER) [5]. Through quantitative simulation of realistically extended non-ideal structures and statistical sampling of different random configurations we can address the LER issue and guide experiments. Using a 3-D, atomistic, quantum mechanical simulator [6] we investigate the performance limitations of single-gate, 5.1nm-wide, p-i-n GNR TFETs with a 30nm gate. We find that source-to-drain tunneling leakage through the gate potential barrier (i) increases with LER and (ii) strongly limits the ON/OFF ratio of the devices to <1000 and SS to 25 mV/dec, even without LER. © 2009 IEEE.