VHDL-based simulation environment for Proteo NoC

  • Sigüenza-Tortosa D
  • Nurmi J
  • 12


    Mendeley users who have this article in their library.
  • 28


    Citations of this article.


The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our network-on-chip (NoC) architecture, called "Proteo". In an intellectual property (IP) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools. The network implements packet switching in a hierarchical topology. We have created a high level model of our network in VHDL, allowing mixed-abstraction level simulation of our synthesizable code for validation.

Author-supplied keywords

  • Communication channels
  • Computer architecture
  • Crosstalk
  • Design methodology
  • Integrated circuit interconnections
  • Intellectual property
  • Libraries
  • Network synthesis
  • Network-on-a-chip
  • Software tools

Get free article suggestions today

Mendeley saves you time finding and organizing research

Sign up here
Already have an account ?Sign in

Find this document

Get full text


  • D. Sigüenza-Tortosa

  • J. Nurmi

Cite this document

Choose a citation style from the tabs below

Save time finding and organizing research with Mendeley

Sign up for free