The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our network-on-chip (NoC) architecture, called "Proteo". In an intellectual property (IP) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools. The network implements packet switching in a hierarchical topology. We have created a high level model of our network in VHDL, allowing mixed-abstraction level simulation of our synthesizable code for validation.
CITATION STYLE
Sigüenza-Tortosa, D., & Nurmi, J. (2002). VHDL-based simulation environment for Proteo NoC. In Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT (Vol. 2002-January, pp. 1–6). IEEE Computer Society. https://doi.org/10.1109/HLDVT.2002.1224419
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