Abstract
An assessment on analog circuit reliability for an advanced 32nm high-k metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed. © 2011 IEEE.
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CITATION STYLE
Chouard, F. R., More, S., Fulde, M., & Schmitt-Landsiedel, D. (2011). An analog perspective on device reliability in 32nm high-k metal gate technology. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 (pp. 65–70). https://doi.org/10.1109/DDECS.2011.5783049
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