Circuit noise effect on sampling clock in frequency-domain radio receiver IF digitization

Abstract

Quantization of the coefficients obtained by the projection of a continuous time signal over an orthogonal space is proposed recently as a new analog to digital (A/D) converting solution. The new A/D technique is to sample the input signal in orthogonal domains which may lead to reduce the degree of signal distortion and significantly less demanding A/D conversion characteristics. As a particular case, the frequency domain analog to digital converter (ADC) overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. Analytical expressions for the A/D conversion with clock jitter error are developed. The computer simulations are presented to show the relationship between sampling clock jitter and A/D conversion performance. ©2009 IEEE.