CMOS VLSI design of low power SRAM cell architectures with new TMR: A layout approach

Abstract

Rapid increase in technology for faster and smarter innovations that smoothens the needs of humans resulting in use of super tech gadgets, which use memory, such as, RAM. To meet the increasing demands, the size is getting reduced and the need to save power arises which reduces the equipment for cooling processes and maintenance. The SRAM cells with lower power dissipation and proper read and write stability is required. This study deals with the design of SRAM cells with low power dissipation in comparison with the conventional SRAM cell design. The SRAM cell design ranges from 3-14T depending on the importance of the application. Here we choose the 6T SRAM cell. The elementary structure uses pass transistor and CMOS, while the proposed SRAM consists of Transmission gates, CMOS, Pseudo-NMOS. This proposed model is compared with two other models of varied 6T SRAM cell. This study also exemplify with the new Triple Modular Redundancy (TMR) techniques with SRAM cell architecture and the layout area with power dissipation results are compared with the existing voting mechanism in 50, 70 90 and 120 nm foundry fabrication process technologies. It is apparent that the proposed voting circuit produces less area at the cost of power dissipation.