Design and analysis of a low power HEMT SRAM cell

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Abstract

Design and evaluation of a novel high speed low power static RAM cell in AlGaAs/GaAs quantum well technology is presented. A current sense amplifier to accompany this cell is also proposed. Simulation results show an access time of 700 ps with standby and active currents of 14μA/bit and 0.29mA bit respectively. The cell area is found to be comparable to that of the corresponding full DCFL cell. © 1995, IEE. All rights reserved.

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Bushehri, E., Bratov, V., Staroselsky, V., Clark, D., & Thiede, A. (1995). Design and analysis of a low power HEMT SRAM cell. Electronics Letters, 31(21), 1828–1829. https://doi.org/10.1049/el:19951278

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