Impact of random telegraph noise on CMOS logic circuit reliability

Abstract

The leading edge products have a feature size of 22 nm in 2014. Designing reliable systems has become a big challenge in recent years. Transistor reliability has a great impact on highly-reliable CMOS circuit operations. Random telegraph noise is one of major recent transistor reliability concerns. First, recent researches on RTN and its impact on circuits are briefly summarized. Then the impact of RTN on CMOS logic circuit reliability is described based on our results from 65 nm and 40 nm test chips. Circuit designers can change various parameters such as operating voltage, transistor size, number of logic stages and substrate bias. The impact of these parameters is clarified in view of RTN-induced CMOS logic delay uncertainty. The impact of RTN can be a serious problem even for logic circuits when they are operated under low supply voltage.