Prediction of interconnect delay in logic synthesis

Abstract

IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design - primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool.