A silicon compiler for massively parallel image processing ASICs

Abstract

A silicon compiler design methodology for massively parallel architecture for image processing is introduced. It starts from an algorithmic description of the application in a language comparable to the GAPP NCR language (GAL) and generates an optimized circuit organized as a 2-D array of 1-b processing elements with minimized resources. The effectiveness of the approach is shown by two examples. The first is an ASIC (application-specific integrated circuit) for two basic mathematical morphology operations, dilation and erosion. The second is an ASIC for convolution. Both have been implemented in a double-aluminum 2-μm CMOS standard cell. In both cases the processor element has been found to be very effective. Considerable area savings have been achieved.