This paper presents a new method to find optimal load impedances of power transistors with a VNA based Load-Pull measurement setup. Most of load pull setups find the optimal load impedance of a device under test (DUT) for a given available input power. If the optimal impedance must satisfy a trade off between several parameters, such as gain compression or power added efficiency, the measurement procedure may become very time consuming. Our method automatically generates a behavioral model of the DUT. Crossing-informations from this model and measurements lead us to the good impedance optimum with a limited number of iterations. © 2007 IEEE.
CITATION STYLE
Reveyrand, T., Gasseling, T., Barataud, D., Mons, S., & Nébus, J. M. (2007). A smart load-pull method to safely reach optimal matching impedances of power transistors. In IEEE MTT-S International Microwave Symposium Digest (pp. 1489–1492). https://doi.org/10.1109/MWSYM.2007.380535
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