9 Design examples INTEGRATEDChapter transceivers are used in many applications. As we have seen in sev- eral tables in 4, the specifications of the oscillators in these transceivers vary considerably when comparing different applications. For example, the phase noise requirements of wireless systems often are much more stringent compared to wired transceivers. This chapter covers four oscillator design examples, and illustrates the design of LC oscillators as well as ring oscillators. The high-frequency oscillators are designed for three different applications. First, the design of a local oscillator for FM radio receivers is highlighted in Section 9.1 [53]. This LC oscillator features a very low power consumption (0.4 mW) while having an excellent spectralpurity The LC oscillator is designed in the IC technology Silicon on Anything (SOA). Second, a 0.9-2.2 GHz ring oscillator [52] and a VHF LC oscillator [54, 162] for a digital satellite receiver is described in Section 9.2 and Section 9.3. Both oscillators are part of a double-loop tuning-system for this satellite receiver. The double-loop tuning-system combines the quadrature property of a two-integrator oscillator with the low-phase-noise property of an LC oscillator [40]. Pulling of the LO and self- reception in the zero-IF architecture of the satellite receiver are minimized, as the two-integrator oscillator is fully integrated and inductorless. Third, the design of a 10 GHz ring oscillator for the Data Clock Recovery (DCR) block in an optical front-end is highlighted in Section 9.4 [124, 125]. One of the 215

216 CHAPTER 9. DESIGN EXAMPLES challenges for this design was to find a suitable topology that would meet the spec- ifications in a BiCMOS process with a 30 GHz and a power budget of 100 mW. Starting off with a two-integrator, the evolution in ring oscillator topologies resulted in a new circuit with active inductive loads. 9.1 A 670���830 MHz LC oscillator for FM radio in SOA The FM radio standard is quite an ancient standard compared to modern digital trans- ceiver standards. However, its use is still extremely wide spread. Increasing the level of integration of FM radio receivers is of interest, since many modern electronic con- sumer products have a built-in FM receiver as an additional selling feature. Examples are mobile phones, MP3 players and PC extension cards. Especially for portable equipment, this FM receiver should be extremely cheap, low power and be fully inte- grated. The first oscillator is a monolithic ultra-low-power LC oscillator running at eight times the FM radio band [53]. 9.1.1 Specifications The nominal target specifications for the FM local oscillator (LO) is listed in Table 9.1. As we know from Table 4.1 on p. 69, the FM radio band starts at 87.5 MHz and extends to 108 MHz. The radio receiver architecture is conventional in the sense that it has a 10.7 MHz IF frequency. In the next section we will see that the quality factor of on-chip inductors is rather low around 100 MHz (the real part is high compared to the imaginary part of the inductor). Therefore, the LO frequency was chosen 8 times higher than the FM radio band plus IF-frequency, and thus ranges from 785 to 950

9.1. A 670���830 MHZ LC OSCILLATOR FOR FM RADIO IN SOA 217 MHz. This LO frequency is divided down (by 8) via a frequency divider to obtain the LO-signal at For FM portable radios a SNR of 60���65 dB is acceptable. The for FM radio can be calculated using (4.9) on p. 76 with rms (assuming a peak frequency deviation of 22.5 kHz) and NBW = 5 kHz. It turns out that must be smaller than -119 dBc/Hz approximately. As is eloquently shown in [3], the phase noise of an oscillator improves 6 dB per division by two of its frequency1. Intuitively this is understandable as the period of the waveform is increased by a factor two after division and the noise is ideally unaffected. Since we have chosen a division factor of 8, the specification of the oscillator around 900 MHz becomes ���119 dBc/Hz + 20 log(8) = ���101dBc/Hz. To demonstrate the suitability of SOA technology2 for low-power oscilla- tors, a challenging power budget of 0.5 mW was chosen. SOA is quite a different technology compared to standard bipolar technologies and is briefly introduced in the next section. 9.1.2 SOA technology SOA technology combines low-power active devices with high Q passives [208]. The on-chip inductors show Q-factors up to 60 @ 2.7 GHz for 1.2 nH inductance. There- fore SOA is well suited for integrated front-ends including RF filters. Varactors for tuning and compensation of the process spread with sufficiently high Q-factors (33 @ 1.9 GHz) also are available. The 13 masks and the lithography keep the process costs low enough, so that even complex filters can be integrated economically. The low power consumption of circuits realized in SOA technology is mainly the result of the removal of the silicon substrate. After processing the wafer is flipped and 1 That is provided the divider is well designed and does not add phase noise. A typical noise floor of a divider for this application is -140 dBc/Hz at 10 kHz offset.

218 CHAPTER 9. DESIGN EXAMPLES glued to an isolating substrate (normally glass). The silicon substrate then is com- pletely removed by etching. Therefore substrate losses and parasitics are minimized, resulting, among other benefits, in the high-Q factor for inductors. The NPN transistor in SOA has a lateral current flow (see Figure 9.1 for a photo of the device [88]). In the vertically oriented emitter area one dimension is defined by the epi-layer thickness This allows emitter base (and collector base) junctions of resulting in very small junction capacitances (0.8 fF and 0.22 fF, respectively). The PNP in SOA is a standard lateral transistor with a minimum emitter area of too (junction capacitances of 0.22 fF). To obtain these minimal parasitics, the silicon substrate has to be removed and replaced by a glass substrate. As a result, the transistor output bandwidth is much closer to transition frequency compared to silicon bulk processes. The maximum supply voltage of the process goes up to 12 V and can be designed by the width of the collector drift region, which is a geometry parameter in the tran- sistors. The process also offers a bipolar logic running down to 0.7 V, having a normalized gate density of and a gate delay of down to 2 ns. A digital design flow environment is available to support mixed-signal design. Figure 9.2 shows a micro-graph of the inductor used in the FM LO design. The distance between the curls is increased for each subsequent curl, to tune each curl to approximately the same frequency. Note that this scaling depends on the initial dis- tance between the inner curls and the inner radius The bridge also deviates from a constant width the outer crossings are smaller to shift the poles together, formed of the inductance of all inner curls and the crossing capacitance. For larger inductors (higher number of turns) this compensation becomes less effective. Hence, the impact of these measures on the Q-factor is between 5% and 12% depending on the inductor���s geometry parameters. Measured Q-factors of three inductors arc shown in Figure 9.3.

9.1. A 670���830 MHZ LC OSCILLATOR FOR FM RADIO IN SOA 219 A single varactor structure is shown in Figure 9.4. It is similar to the emitter-base complex of the NPN transistor and allows the exchange of Q versus by design parameters. These basic cells are put together by a varactor layout generator to build up larger arrays. The maximum Q-factors mentioned can be obtained in narrow band systems. In the varactor cell used in the FM LO the length of the low-doped drift region (dr) is After realization of the VCO design, new layout design rules allowed a minimum drift region of This results in higher Q-factors as can be seen in Figure 9.5. Given the combination of the specified value in Table 9.1 and the power budget of 0.5 mW, it is clear that we can only achieve this with an LC oscillator. 9.1.3 Oscillator design