A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

Abstract

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage (VTH) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (VDD) of 0.6 V in 40 nm CMOS technology with this scheme. © 2011 IEEE.