Next generation Intel® core micro-architecture (Nehalem) clocking

Abstract

This paper describes the core and I/O clocking architecture of the next generation Intel® Coremicro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and ±15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intel® QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s. © 2006 IEEE.