A 1000FPS@128×128 vision processor with 8-bit digitized I/O

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Abstract

This paper demonstrates the use an of mixed-signal processing elements, operating according to a SIMD computing scheme, to solve real-time vision problems with a single ship. The prototype, designed in a 0.35μm fully digital CMOS technology, contains ∼ 3.75 mill. Transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. The chip incorporates different light sensing mechanisms, both integration and log-compression types, to avoid the need for an additional imager in a vision system based on it. Though processing tasks are implemented using analog building blocks, the chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120Mbytes/s. Experimental results show that frame rates of 1000FPS can be achieved under typical room illumination conditions. At such high speed, the chip is capable to execute, concurrently to image acquisition, around 150 image filtering operations, additions, or Boolean combinations per frame. This feature, together with the possibility of executing sequences of user-selectable instructions (stored on a program memory), and storing intermediate results (up to 8 gray-scale images) makes the chip a true general-purpose sensory/processing device. © 2003 IEEE.

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APA

Liñán-Cembrano, G., Rodríguez-Vázquez, A., Domíguez-Castro, R., & Espejo-Meana, S. (2003). A 1000FPS@128×128 vision processor with 8-bit digitized I/O. In European Solid-State Circuits Conference (pp. 61–64). https://doi.org/10.1109/ESSCIRC.2003.1257072

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