3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Abstract

A quasi-complementary BiCMOS gate for low voltage supply is applied to a 3.3-V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISC’s. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3-μm BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V.