Acceleration of fractal image compression using the hardware-software co-design methodology

Abstract

Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program hardware modules, but also contain one or more embedded processors, allowing the creation of complete systems inside a single chip (SoC). The use of hardware and software components in a single electronic system allows to combine the flexibility offered by software and the high computing power and parallelism of hardware. This paper describes a Hardware-Software Co-Design (HSC) of FIC which improves the compression time, obtaining an acceleration factor between 6.6 and 8.5. The system was built on a SoC based on an FPGA. © 2009 IEEE.