Abstract
In this study, we compared sensing margin according to the back gate bias and body doping concentration. We achieved large sensing margin of 62 uA/um at LG = 87 nm and demonstrated sensing margin of 45 uA/um with L G = 47 nm that is the smallest device ever reported for the floating body RAM. For the scaling down to the sub 50 nm gate length, we should reduce the body thickness for the SCE with optimum body doping condition . Possibility of scaling down with the capacitor-less RAM is shown to the sub 50 nm from this result. ©2007 IEEE.
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CITATION STYLE
Yun, E. J., Song, H. J., Hong, S. I., Kim, S. H., Choi, Y. L., Bae, H. J., … Park, D. (2007). Analysis of sensing margin in silicon-On-ONO (SOONO) device for the capacitor-less RAM applications. In Proceedings - IEEE International SOI Conference (pp. 103–104). https://doi.org/10.1109/SOI.2007.4357873
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