Application of a novel active envelope load pull architecture in large signal device characterization

Abstract

This paper presents the large signal characterization of an on-wafer PHEMT device using a novel closed loop active envelope load pull architecture. The architecture addresses active load-pull measurement system stability issues associated with previously realized closed loop architectures by utilizing a feedback loop at envelope frequencies. It solves, for the first time, many of the problems associated with existing active load pull architectures. Stability of the system is demonstrated and evaluated using device measurements. Example, load pull contour plots and Pout Vs Pin achieved by the systems are shown and analyzed. The results suggest that the new approach, by overcoming the problems of existing active load pull architectures, opens up the possibility of their utilization in high speed production test.