Automatic sizing of power/ground (P/G) networks in VLSI

Abstract

The authors present a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while electromigration and voltage drop constraints are fulfilled. The algorithm for sizing P/G wires has been implemented, and a preliminary version is being used as a part of a building block layout system. The algorithm is found to run 50% faster than the best methods reported for tree-type network topologies.