Chip level reliability on SOI embedded memory

Abstract

A novel structure of stacked-capacitor cell with an easy wiring process, which utilizes the virtual flat surface at the bottom of SOI of stacked-capacitor cells, is described. The virtual flat surface is brought into a real surface by reversing capacitor and polishing the substrate with bonded-SOI technology. This memory cell is named as an Embedded memory SOI process (EMSP). The problems of capacitor formation under SOI structure are analyzed, and process limitation to improve embedded memory SOI process are confirmed using the 16M SOI DRAM with 0.35 μm design rule technology.