Circuit failure prediction and its application to transistor aging

Abstract

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by Negative Bias Temperature Instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design. © 2007 IEEE.