Computer-Aided Design and Scaling of Deep Submicron CMOS

Abstract

A simulation tool-box and its applications to computer-aided design and scaling of deep submicron CMOS are presented. The simulation tools are grouped around a mixed level device/circuit simulator and cover a wide range of applications, starting from Monte Carlo device simulation up to VLSI circuit simulation. Due to the mixed level approach, fast table models and accurate numerical models can be combined simultaneously in a single circuit simulation. The circuit simulations are based on the numerical solution of the semiconductor transport equations so that device and circuit characteristics can be accurately represented as functions of technology parameters, even in the deep submicron region. The application of the tool-box is demonstrated for some examples from the fields of device design and SRAM scaling. Gate-drain overlap and junction depth of 0.4-pm devices are optimized with respect to circuit performance and device degradation. Different drain structures and supply voltages for 0.25-µm devices are compared. Furthermore, scaling of CMOS SRAM’s from 0.7 to 0.4 pm and finally to 0.25-pm gate length is simulated. The relevance of device structure, design rules, and supply voltage for speed, power dissipation, and chip area are pointed out and their influence on circuit performance is predicted. © 1993 IEEE