Depletion isolation effect of surrounding gate transistors

Abstract

Sub-half-micron surrounding gate transistors (SGT's) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g. 0.6 μm SGT) by using the lower diffusion layer of the Si pillar as drain and applying sufficiently high voltage I-V characteristics inherent to fully-depleted devices (i.e. subthreshold swing as low as 60 mV/dec. lowered threshold voltage independent of substrate bias voltage) were observed (depletion isolation effect). © 1997 IEEE.