Design and analysis of fast low power SRAMs

Abstract

This thesis explores the design and analysis of Static Random Access Memories(SRAMs), focusing on optimizing delay and power. The SRAM access path is split intotwo portions: from address input to word line rise (the row decoder) and from word linerise to data output (the read data path). Techniques to optimize both of these paths areinvestigated.We determine the optimal decoder structure for fast low power SRAMs. Optimaldecoder implementations result when the decoder, excluding the predecoder, isimplemented as a binary tree. We find that skewed circuit techniques with self resettinggates work the best and evaluate some simple sizing heuristics for low delay and power.We find that the heuristic of using equal fanouts of about 4 per stage works well even withinterconnect in the decode path, provided the interconnect delay is reduced by wire sizing.For fast lower power solutions, the heuristic of reducing the sizes of the input stage in thehigher levels of the decode tree allows for good trade-offs between delay and power.The key to low power operation in the SRAM data path is to reduce the signal swingson the high capacitance nodes like the bitlines and the data lines. Clocked voltage senseamplifiers are essential for obtaining low sensing power, and accurate generation of their sense clock is required for high speed operation. We investigate tracking circuits to limitbitline and I/O line swings and aid in the generation of the sense clock to enable clockedsense amplifiers. The tracking circuits essentially use a replica memory cell and a replicabitline to track the delay of the memory cell over a wide range of process and operatingconditions. We present experimental results from two different prototypes.Finally we look at the scaling trends in the speed and power of SRAMs with size andtechnology and find that the SRAM delay scales as the logarithm of its size as long as theinterconnect delay is negligible. Non-scaling of threshold mismatches with process scal-ing, causes the signal swings in the bitlines and data lines also not to scale, leading to anincrease in the relative delay of an SRAM, across technology generations.The wire delaystarts becoming important for SRAMs beyond the 1Mb generation. Across processshrinks, the wire delay becomes worse, and wire redesign has to be done to keep the wiredelay in the same proportion to the gate delay. Hierarchical SRAM structures have enoughspace over the array for using fat wires, and these can be used to control the wire delay for4Mb and smaller designs across process shrinks.