Design and performance analysis of 1 bit full adder using GDI technique in nanometer era

Abstract

In this paper, the low power and high performance full adder using 11 transistors has been proposed. The GDI (gate diffusion input) technique has been used for simultaneous generation of XOR gate. The main idea behind the designing of this 11 transistors full adder to improve the performance of 10 transistors full adder design mentioned in literature by sacrificing a transistor count. While the proposed full adder has negligible area overhead, it has improved the power consumption of the circuit when compared with the 10T full adder circuit. We have simulated these two full adders by using cadence virtuoso tool at supply voltages range from 0.4V to 1.2V at 27 °C. © 2012 IEEE.