Design for testability: Today and in the future

Abstract

With continued increases in densities of technologies, testing continues to be a significant impediment to productivity if not addressed properly. In this presentation we will review the current techniques with a particular emphases on today's Scan designs. This will entail distinguishing the differences between scan techniques, since all scans are not created equal. From this point the Testibility Standards will be discussed; this will include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in todays technologies. The Delay Fault models will be discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, Self Test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular Self-Testing design techniques will be shown. The presentation will be concluded by a discussion of the interaction of testing and synthesis., Finally, the role of Testing will be explored in the new design environments which includes Hardware Software Codesign.