Digital component separator for future w-CDMA-LINC transmitters implemented on an FPGA

Abstract

This paper presents the implementation of a Digital-Component-Separator (DCS) for a LINC-transmitter (linear amplification using nonlinear components) on an FPGA (field programmable gate array). It investigates and estimates the bandwidth requirements for such a LINC system. The influence of bandwidth limitations on a digitally based LINC-transmitter for W-CDMA utilization is studied by simulations. Furthermore a LINC transmitter is proposed which employs a flexible image-reject-or a direct up-conversion-architecture for transmission of single or combined multi-carrier/channel W-CDMA signals using the phase-modulation approach. The sampling frequency can be chosen at a value up to 32 times (122.88MHz) the symbol rate of the W-CDMA chip rate of 3.84Mbits/s. Measurement results for a LINC transmitter are presented and discussed. © 2005 Copernicus GmbH.