An Experimental 1.5-V 64-Mb DRAM

Abstract

Low-voltage circuit technologies for higher density DRAM's, as well as their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage, are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns is achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V cc voltage generator with a current-mirror amplifier and a tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades is realized. A word-line driver with a charge-pump circuit is developed to achieve a high boost ratio. A ratio of about 1.8 is obtained from a power supply voltage as low as 1.0 V. A 1.28-μm 2 crown-shaped stacked-capacitor (CROWN) cell is also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5-V 64-Mb DRAM is then designed and fabricated with these technologies and 0.3-μm electron-beam lithography. A typical access time of 70 ns is obtained and a further reduction to 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAM's, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAM's. This indicates that a low-voltage battery operation is a promising target for future DRAM's. © 1991 IEEE