Exploiting data parallelism in signal processing on a dataflow machine

Abstract

This paper will show that the massive data parallelism inherent to most signal processing tasks may be easily mapped onto the parallel structure of a data flow machine. A special system called STRUCTFLOW has been designed to optimize the static data flow model for hardware efficiency and low latency. The same abstractions from the general purpose data flow model that lead to a quasi systolic operation of the processing elements make explicit flow control of the data tokens as they pass through the arcs of the flow graph obsolete. We will describe the architecture of the system and discuss the restrictions on the structure of the flow graphs.