Factoring logic functions using graph partitioning
- ISBN: 0780358325
- DOI: 10.1109/ICCAD.1999.810648
Abstract
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. The independent stage includes logic operations such as decomposition, extraction, factoring, substitution and elimination. These operations are done with some kind of division (Boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals. In this paper, we present an algorithm for factoring that uses graph partitioning rather than division. Central to our approach is to combine this with the use of special classes of Boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. Our method has been implemented in the SIS environment, and an empirical evaluation indicates that we usually get significantly better results than algebraic factoring and are quite competitive with Boolean factoring but with lower computation costs
Factoring logic functions using graph partitioning
Martin C. Golumbic and Aviad Mintz
Department of Mathematics and Computer Science,
Bar Ilan University, Ramat Gan 69978, Israel
Abstract
Algorithmic logic synthesis is usually carried out in two stages,
the independent stage where logic minimization is performed on
the Boolean equations with no regard to physical properties and
the dependent stage where mapping to a physical cell library
is done. The independent stage includes logic operations like
Decomposition, Extraction, Factoring, Substitution and Elimi-
nation. These operations are done with some kind of division
(boolean, algebraic), with the goal being to obtain a logically
equivalent factored form which minimizes the number of liter-
als.
In this paper, we present an algorithm for factoring that uses
graph partitioning rather than division. Central to our approach
is to combine this with the use of special classes of boolean func-
tions, such as read-once functions, to devise new combinatorial
algorithms for logic minimization. Our method has been im-
plemented in the SIS environment, and an empirical evaluation
indicates that we usually get signi cantly better results than al-
gebraic factoring and are quite competitive with boolean factor-
ing but with lower computation costs.
1 Introduction
Algorithmic logic synthesis is usually done in two stages, the
independent stage where logic minimization is performed on
the Boolean equations with no regard to physical properties and
the dependent stage where mapping to a physical cell library is
done. The independent stage includes such logic operations as
Decomposition, Extraction, Factoring, Substitution and Elimi-
nation. These operations are done with some kind of division
(boolean, algebraic) [4].
The objective of factorization is to represent a boolean func-
tion in a logically equivalent factored form but with a minimum
number of literals. This type of optimization will yield a mini-
mum area taken by realization of this function. Algebraic algo-
rithms for factorization are known [8, 9] and are widely used in
commercial environments due to their speed. On the other hand,
Boolean factoring [9] is not widely used because of its compu-
tational complexity even though it gives much better results.
In this paper, we investigate an algorithmic method for fac-
toring that uses graph partitioning rather than division. Our
method is a generalization of techniques for the so called read-
once functions
1
[3], a special family of monotone Boolean func-
tions, also known as non-repeatable tree (NRT) functions [6]. In
our study of this method, we obtain better results than algebraic
factoring in most test cases and very competitive results with
Boolean factoring with less computation time.
2 The cluster intersection graphs of
SOP and POS forms
A standard canonical form for representing a Boolean function
is as a sum of products (SOP) also known as Disjunctive Normal
Form (DNF). The formula F
1
= aq+acp+ace , in the example
from the footnote, is in SOP form. Dual to this, is the canon-
ical form known as product of sums (POS) also called Con-
junctive Normal Form (CNF), which for our example would be
g = F
3
= a (q+ c) (q+ p+ e). We assume that a given form
is simpli ed, that is, a SOP is the sum of prime implicants of the
function, and a POS is the product of prime explicants. A prime
implicant (resp., prime explicant) is a minimal product (resp.,
sum) of literals whose truth implies the truth of the function and
whose removal from the formula would change the function. In
general, such an SOP or POS form is not unique, although for
read-once functions it is unique.
The parse tree (or computation tree) of an SOP (resp., POS)
may be regarded as a two level circuit with the literals labeling
the leaves of the tree, the level one nodes being the operation (resp., +) and the root being the operation + (resp., ). The
level one nodes partition the leaves (literals) into subsets which
1
A Boolean function f is called a read-once function if it has a factored form
in which each variable appears exactly once. In logic synthesis, one traditional
measure of the complexity of a logic circuit is the number of literals. In this
sense, a read-once formula is the best possible since no variable is repeated. For
example, the function g = F
1
= aq + acp + ace is a read-once function since
it can be factored into the read-once formula g = F
2
= a(q+ c(p+ e)).The
reason that read-once functions are also known as non-repeatable tree functions
is that the parse tree of a read-once formula has no variable repeated. Read-once
functions have interesting special properties [3, 5] and according to [6] account
for a large percentage of functions which arise in real circuit applications. They
have also gained recent interest in the eld of computational learning theory.
1
0-7803-5832-X /99/$10.00 '1999 IEEE.
0-7803-5832-5/99/ $10.00 © 1999 IEEE
195
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