Abstract
We present fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchial schematic design. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are down stream from the compilation process. The batch algorithm uses a preorder traversal of the design hierarchy to derive the netlist. The incremental algorithm trims this traversal to only those paths leading to changes in the netlist. For most user modifications the netlist can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no preceivable delay to the user. © 1991 IEEE
Cite
CITATION STYLE
Jones, L. G. (1991). Fast Batch and Incremental Netlist Compilation of Hierarchical Schematics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(7), 922–931. https://doi.org/10.1109/43.87602
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