Introducing redundancy in field programmable gate arrays

Abstract

A redundancy scheme and circuitry for Field Programmable Gate Arrays (FPGA's) are proposed for the first time. The scheme requires the modification to the wiring resource segmentation and the addition of the spare rows and the selector circuits. In this paper an improved yield gross product is quantitatively studied. The disadvantages caused by this architecture are also discussed such as an area overhead and speed degradation. It is concluded that in this redundancy scheme, the sufficient number of spare rows is one or two for practical case and the gross yield product can be doubled at an early stage of production. The proposed scheme can be applicable to wide range of FPGA architecture.