A low cost single-cycle router based on virtual output queuing for on-chip networks

Abstract

The communication latency of Network-on-Chip (NoC) is one of the factors that significantly impacts on the application performance on System-on-Chips. To reduce the NoC latency, we propose a low latency architecture of router, which utilizes virtual output queuing (VOQ) to shorten the processing time of a packet transfer. Based on taking advantage of VOQ in buffering, the number of pipeline stages of a packet transfer can be reduced to two stages of switch allocation and switch traversal. By speculatively implementing these stages in a parallel fashion, the router can perform a packet transfer in only one clock cycle. In addition, a multiple VOQ architecture that each input port maintains more than one queue for each output channel is also proposed for improving the throughput of router. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that in a 4×4 two-dimensional mesh network, the proposed router reduces the communication latency by 25% and cost of area by 67.3% as compared to the look-ahead speculative virtual channel router. © 2010 IEEE.