Chapter 5
Optimizing Power @ Design Time – Architecture, Algorithms,
and Systems
Jan M. Rabaey
Dejan Markovi
Optimizing Power @ DesignTime
Architectures, Algorithms, and Systems
Slide 5.1
This chapter presents
power–area–performance
optimization at the higher
levels of the design hierar-
chy – this includes joint
optimization efforts at the
circuit, architecture, and
algorithm levels. The
common goal in all these
optimizations is to reach
a global optimum in the
power–area–performance
space for a given design.
The complexity of global optimization involving variables from all layers of the design-
abstraction chain can be quite high. Fortunately, it turns out that many of the variables can
be independently tuned, so a designer can partition optimization routines into smaller
tractable problems. This modular approach helps gain insight into individual variables
and provides a way to navigate top-level optimization through inter-layer interactions.
Chapter Outline
The architecture/system trade-off space
Concurrency improves energy-efficiency
Exploring alternative topologies
Removing inefficiency
The cost of flexibility
Slide 5.2
The goal of system-level
power (energy) optimiza-
tions is to transform the
energy–delay space such
that a broader range of
options becomes available
at the logic or circuit levels.
In this chapter, we classify
these transformations into
a number of classes: the
usage of concurrency,
considering alternative
topologies for the same
J. Rabaey, Low Power Design Essentials, Series on Integrated Circuits and Systems,
DOI 10.1007/978-0-387-71713-5_5,  Springer ScienceþBusiness Media, LLC 2009
113

function, and eliminating waste. The latter deserves some special attention. To reduce the
non-recurring expenses and to encourage re-use, programmable architectures are becoming
the implementation platform of choice. Yet, this comes at a huge expense in energy efficiency.
The exploration of architectures that combine flexibility and efficiency is the topic of the last part
of this chapter.
Motivation
Optimizations at the architecture or system level can
enable more effective power minimization at the circuit
level (while maintaining performance), such as
– Enabling a reduction in supply voltage
– Reducing the effective switching capacitance for a given function
(physical capacitance, activity)
– Reducing the switching rates
– Reducing leakage
Optimizations at higher abstraction levels tend to have
greater potential impact
– While circuit techniques may yield improvements in the 10–50%
range, architecture and algorithm optimizations have reported
power reduction by orders of magnitude
Slide 5.3
The main challenge in hier-
archical optimization is the
interaction between the
layers. One way to look at
this is that optimizations at
the higher abstraction layers
enlarge the optimization
space, and allow circuit-
level techniques such as sup-
ply voltage or sizing to be
more effective. Other optimi-
zations may help to increase
the computational efficiency
for a given function.
Circuit Optimization Limited in Range
Case study: Tree adder
Result of joint (V
DD
, V
TH
, W )
optimization:
– 65% of energy saved
without delay penalty
– 25% smaller delay
without energy cost
Need higher-level optimizations for larger gain
Lessons Learned from Circuit Optimization
D/D
ref
E
/
E
r
e
f
0 0.5 1 1.5
1.5
1
0.5
0
65%
ref
Ref: min delay at nominal V
DD
, V
TH
25%
[Ref: D. Markovic, JSSC’04]
Slide 5.4
Consider the energy–delay
design space exploration
exploiting size as well as
supply and threshold vol-
tages as parameters, as dis-
cussed in Chapter 4. For a
64-bit tree adder and a
given technology, a par-
eto-optimal energy–delay
curve is obtained showing
some nice energy or delay
improvements over the
reference design. Yet the
overall optimization space
is restricted by the topology
of the adder. Larger energy
savings could be obtained
by choosing a different
adder topology such as a ripple adder. To accomplish these larger gains (both in delay and energy),
accompanying transformations at the micro-architecture or system architecture level are needed.
Over the past decades, it has been shown that this can lead to orders of magnitude in energy-
efficiency improvement quite impressive compared to the 30% range that is typically obtained at
the circuit level. In this chapter, we present a methodological approach to extend the techniques
introduced so far to the higher abstraction layers.
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