A low power high performance CMOS voltage-mode quaternary full adder

Abstract

Multiple-valued logic, despite of all its theoretical potentialities, has not provided real advantages for arithmetic circuits when compared to the binary equivalent ones until now. This paper shows a new efficient method to implement quaternary logic arithmetic circuits using multi-threshold transistors, where 3 power supply lines are used to perform quaternary circuits with low power consumption and high performance. As a demonstration, a quaternary full adder is described in TSMC 0.18μm technology and compared to regular binary circuits, presenting a 76% reduction in power consumption, and an improvement of 15% regarding speed with a 20% area overhead.