Low-power dividerless frequency synthesis using aperture phase detection

Abstract

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eUminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eUminatiDI the divider. The PLL's loop bandwidth is measured to be 6 MHz, with a reference spurious level of -47 dBc. The lront-end receiver, including the synthesizer, is fabricated in a 0.5-μm, triple-metal, single-poly CMOSprocess and operates on a 1.5-V supply.