A network processor architecture for very high speed line interfaces

Abstract

A network processor architecture that can be used for very high speed line interfaces of carrier-class backbone routers and switches has been developed. The architecture is based on large-scale on-chip multi-processing using static resource scheduling to meet the requirements so that multi-processing works efficiently in packet forwarding. Since advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism as well as flexible header handling. The architecture sevaluated by using a prototype hardware design and two typical application examples: IP packet forwarding and ATM/IP multi-layer switching with per-VC/per-flow queuing mechanism. These evaluations show that the architecture can provide various advanced functions for 2.4 Gbps line interfaces even in a common 0.25 μm standard cell based LSI design. It can also provide 10 Gbps packet forwarding for basic IP packet handling.