Abstract
In this paper we describe architecture for H.264/AVC video decoder. This architecture exploits NoC (Network-on-Chip) for data transport between decoder blocks and is optimized for efficient processing, simple data flow and management. Proposed solution enables flexible device structure configuration and supports testing and verification environments. The presented original architecture is general and can be adopted to develop any modern video and audio codec. Copyright © 2008 by Department of Electronics, AGH University of Science and Technology.
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CITATION STYLE
Łuczak, A., Garstecki, P., Stankiewicz, O., & Stepniewska, M. (2008). Network-on-chip based architecture of H.264 video decoder. In ICSES’08 - ICSES 2008 International Conference on Signals and Electronic Systems, Proceedings (pp. 419–422). https://doi.org/10.1109/ICSES.2008.4673454
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