Abstract
This paper describes a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrated through a simulation example involving a CMOS process adopted from an industrial line. © 1991 IEEE
Cite
CITATION STYLE
Low, K. K., & Director, S. W. (1991). A New Methodology for the Design Centering of IC Fabrication Processes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(7), 895–903. https://doi.org/10.1109/43.87599
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