Portable parallel test generation for sequential circuits

Abstract

We report a new parallel test generation algorithm, Proper TEST, for sequential circuits that is portable across a range of MIMD parallel architectures. It uses prioritized execution to ensure consistent speedups as the number of processors is increased. This consistency is achieved without loss in fault coverage with increase in number of processors. This also enables the use of parallel processing to improve the fault coverage when the execution time is bounded. Results on ISCAS 89 benchmark programs are provided on a shared memory machine, a message passing machine and a network of Sun workstations. Proper TEST was run unchanged on these different architectures.