Predictable Routing
Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh
Department of Electrical and Computer Engineering
Northwestern University, Evanston, IL 60208
kastner,elib,majid@ece.northwestern.edu
, Abstract
Predictable routing is the concept of using prespecified patterns to route
a net. By doing this, we allow an more accurate prediction mechanism
for metrics such as congestion and wirelength earlier in the design flow.
Additionally, we can better plan the routes, insert buffers and perform
wire sizing earlier. With comparable routing quality, we show that we
can predictably route up to 80% of a selected subset of nets. Also, we
introduce methods for finding a group of nets which can be predictably
routed.
1 Introduction
The process of routing can be divided into two subproblems, global and
detailed routing. Global routing decomposes the routing problem into
smaller, manageable routings for the detailed router. Specifically, the
global router finds a rough path for each net while trying to reduce
the chip size, shortening the wire length and distributing the congestion
across the routing area, among other things [5, 7, 111. Detailed routing
uses the results of global routing to find an exact realization of the in-
terconnections in VLSI circuits. The focus of this paper is on the global
routing problem.
Predictable routing is the idea of using prespecified patterns to route
a net. This is particularly useful for CAD tools preceding global routing
in the design flow. For example, most placement tools use quick routing
metrics to find congestion and wirelength information. In this paper, we
develop quick routing methods that do not affect the quality of the rout-
ing solution. Since we know these metrics will not affect the routing,
congestion and wirelength are more accurately modeled earlier in the
design flow. Also, since we know the route of a net, we can start wire
sizing, wire planning and optimally add buffers' without going through
the time consuming process of routing. As fabrication technology moves
into deep submicron (DSM) device sizes, local interconnect effects have
an increasingly dominant role [2]. These effects include increasing inter-
connect capacitance and resistance. Logic and behavioral synthesis tools
have no accurate way of modeling interconnect. Predictable routing pro-
vides these tools with an accurate interconnect prediction mechanism.
These ideas are further explained in Section 3.1.
In this paper, we propose modifications to the global routing algo-
rithm. These modifications allow nets to be predictably routed with
little or no loss in the quality of the global routing solution. In Section
2, we discuss the idea of congestion and briefly review maze routing. Sec-
tion 3 introduces the idea of predictable routing through pattern routing.
We discuss the 1-density routing problem which uses the pattern routing
concept. In Section 4, we present methods for finding a subset of nets
which can be predictably routed. We conclude in Section 5.
2 Preliminaries
A grid g m p h is a graph G(V,E) such that each vertex corresponds to
a point in a plane. See Figure 1 for further explanation. A net =
'If we know the net topology the complexity of buffer insertion for
delay becomes polynomial time solvable [4].
{ (x i , yi, ), (12, yz), (23, y3), ..., (zn, yn)} is an unordered set of points on
a grid graph. A single point of the net is referred to as a terminal. A
routing of a net is a set of grid edges such that the terminals are fully
connected. The route edges of a net are the set of edges used in the
routing of that net.
A global bin is a rectangular partition of the chip. By partitioning
the chip into many rectangular regions and placing the cells into these
regions, we have a placement using global bins. The boundaries of the
global bins are global bin edges.
Global
Edges
Figure 1: (a) Placement of cells into global bins. (b) The corre-
sponding grid graph.
In this paper, we assume that a global placement of cells and their
interconnections are given by some placement engine (our experiments
used Dragon [6] which is comparable in quality to commercial version of
Timberwolf [13]). The cells are placed into global bins and each cell is
assumed to be placed in the center of the global bin. Looking at Figure
1, it is easy to see that the global bins and edges can be transformed into
a grid graph. The interconnections between the cells can be modeled by
nets.
2.1 Congestion
Congestion in a layout means that there are too many nets routed in a
local area. This causes difficulty for the detailed router as it may not
find a feasible routing solution. We want to evenly distribute the routing
across the total chip area.
The congestion of an edge is the number of nets routed over a global
bin edge. The capacity (also referred to as supply) of edge e is ce. It is
the maximum number of nets that can be routed over e. ce is a fixed
value that is based on the length of the edge and the technology used in
creating the chip. The routing demand of e, specified as d e , is defined as
the number of route edges crossing e . Similarly, the demand of a vertex
v is d,. Here the demand corresponds to the number of routes that pass
though the vertex w (equivalently the global bin w). An edge is overflown
if and only if the de > ce. Formally, the overflow of an edge is:
t is a threshold value which allows de to go above ce without an overflow
penalty. t is included because you can often route up to t nets though
neighboring bins without affecting the congestion of those bins. t is
0-7803-6445-7/00/$10.00 0 2000 IEEE 110