Process dependent static cache partitioning for real-time systems

Abstract

The author investigates the use of a priori knowledge of program behavior to partition an instruction cache of size C into a static partition of size S and an LRU partition of size C-S. The value of S is task-dependent and is nonzero for most programs running on the system. Example programs are presented, and their behavior in various size caches is discussed. Cache partitions are generated and evaluated to determine the increase in cache performance and predictability. A high-level hardware design is presented that provides the desired partitioning scheme.