PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers (1982)
- ISSN: 00189340
- DOI: 10.1109/TC.1982.1675906
Available from ieeexplore.ieee.org
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Abstract
The PUMPS architecture consists of P task processing units (TPU) which share a pool of special peripheral processors, VLSI functional units, and a common two-dimensional shared memory (SM) via a block transfer oriented interconnection network. A shared cache is provided between the TPU's and SM for efficient MIMD interprocessor communication. The SM is also connected via a backend database management network (BDMN) with distributed control to the file memories, which are disk-based database storage devices.
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