RT level test scheduling

Abstract

The paper describes a new model of exploiting parallelism in testing of VLSI circuits. A circuit at the register transfer level is denoted as an RTL circuit. The model utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during an RTL circuit test scheduling are presented. The problem of concurrent test application is transformed to the one of TACG coloring and covering its nodes. Thus, the graph theory algorithms can be utilized for an RT level test scheduling. The way how to use a TACG for an RTL circuit modification is also presented. The paper offers a methodology that can be utilized during VLSI circuit design process, the final goal of which is to reduce the overall test application time of an RTL circuit. Keywords: Design for testability, RT level test scheduling, test application, concurrent testing.