Scheduling strategies for non-binary LDPC codes

Abstract

Non-binary LDPC codes are promising error correcting codes for short and moderate block lengths. These codes demonstrate interesting performances in high order fields, though are more complex to decode. As for binary LDPC codes, decoding scheduling can be optimized to improve performance. In this paper, a simulation-based approach is used for different scheduling policies in the non-binary case in order to point out possible performance gains for these codes. An optimization of decoding scheduling is also proposed and exhibits about 20% complexity reduction in error-floor region, thus promising interesting gains if combined with advanced dynamic scheduling strategies. ©2009 IEEE.