A Surface-Charge Random-Access Memory System

Abstract

This paper presents a surface-charge storage cell suitable for word-organized dynamic random-access memory and discusses its operation in a memory system. Experimental results and computer simulations of the readout process on a 4 X 8 array using this cell are given. A sensitive stable sense-and-refresh amplifier, suitable for use with this memory cell is also described. Simulations of a 4096-bit chip with a storage cell density of 2.5 mils2/bit using this refresh amplifier predict a cycle time of 250 ns. Copyright © 1972, by The Institute of Electrical and Electronics Engineers, Inc.