Abstract
In this paper, we present optimized methodology for Intra-task voltage scheduling. Our proposed method gets data flow and control flow of application that represents coloration between different parts of the application at the early stage of design using UML-RT model and decides to schedule processor's voltage. By applying this technique on JPEG encoder system experimental results show reduction in energy consumption by 18-54 % over common Intra-DVS algorithm. © 2007 IEEE.
Cite
CITATION STYLE
Neishaburi, M. H., Daneshtalab, M., Nabi, M., & Mohammadi, S. (2007). System level voltage scheduling technique using UML-RT model. In 2007 IEEE/ACS International Conference on Computer Systems and Applications, AICCSA 2007 (pp. 500–505). https://doi.org/10.1109/AICCSA.2007.370928
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